LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 879
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Fig 141. Format and states in the Master Receiver mode
successful
transmission to
a Slave
transmitter
next transfer
started with a
Repeated Start
condition
Not Acknowledge
received after the
Slave address
arbitration lost in
Slave address or
Acknowledge bit
arbitration lost
and addressed
as Slave
DATA
n
08H
S
A
from Master to Slave
from Slave to Master
any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I
SLA
2
C bus
All information provided in this document is subject to legal disclaimers.
R
MR
Rev. 00.13 — 20 July 2011
40H
48H
A OR A
68H 78H B0H
A
A
A
38H
P
DATA
other Master
continues
other Master
continues
50H
A
to corresponding
states in Slave
DATA
mode
Chapter 37: LPC18xx I2C-bus interface
58H
38H
A
A
10H
P
S
other Master
continues
SLA
mode, entry
to Master
UM10430
transmit
= MT
© NXP B.V. 2011. All rights reserved.
W
R
879 of 1164
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