LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 899

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
38.4 General description
38.5 Pin description
38.6 Register description
<Document ID>
User manual
Basic clocking for the A/D converters is provided by the APB clocks
(CLK_APB3_ADC0/1). A programmable divider is included in each converter to scale this
clock to the 4.5 MHz (max) clock needed by the successive approximation process. A fully
accurate conversion requires 11 of these clocks.
Table 826
Table 826. ADC pin description
The register addresses for the ADC0 are shown in
Table 827. Register overview: ADC0 (base address 0x400E 3000)
Pin
ADC[7:0]
ADCTRIG0 Input
ADCTRIG1 Input
VDDA
VSSA
Name
CR
GDR
-
•
•
•
•
•
•
•
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3.3 V.
10 bit conversion time  2.44  s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
gives a brief summary of each of ADC related pins.
Access Address
R/W
R0
-
Type
Input
Power
Ground
All information provided in this document is subject to legal disclaimers.
offset
0x000
0x004
0x008
Rev. 00.13 — 20 July 2011
Description
Analog Inputs. The A/D converter cell can measure the voltage on any of
these input signals. The inputs are shared between ADC0 and ADC1.
Remark: The ADC0 pin is shared with the DAC0 pin.
Trigger inputs to the ADC0/1.
Trigger inputs to the ADC0/1.
Analog Power. Also voltage reference VREF for both ADCs.
Analog ground.
A/D Control Register. The AD0CR register
A/D Global Data Register. Contains the result
Reserved.
Description
must be written to select the operating mode
before A/D conversion can occur.
of the most recent A/D conversion.
Table 827
Chapter 38: LPC18xx 10-bit ADC0/1
UM10430
© NXP B.V. 2011. All rights reserved.
-
Reset
value
0x0000 0000
-
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