LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 256
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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15.5.1.10 Pin interrupt status register
15.5.2.1 Grouped interrupt control register
15.5.2.2 GPIO grouped interrupt port polarity registers
15.5.2 GPIO GROUP0/GROUP1 interrupt register description
Reading this register returns ones for pin interrupts that are currently requesting an
interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones
to this register clears both rising- and falling-edge detection for the pin. For level-sensitive
pins, writing ones inverts the corresponding bit in the Active level register, thus switching
the active level on the pin.
Table 180. Pin interrupt status register (IST address 0x4008 7024) bit description
Table 181. GPIO grouped interrupt control register (CTRL, addresses 0x4008 8000 (GROUP0
The grouped interrupt port polarity registers determine how the polarity of each enabled
pin contributes to the grouped interrupt. Each port n (n = 0 to 7) is associated with its own
port polarity register, and the values of all registers together determine the grouped
interrupt.
Bit
7:0
31:8
Bit
0
1
2
31:3
Symbol Description
PSTAT
-
Symbol
INT
COMB
TRIG
-
INT) and 0x4008 9000 (GROUP1 INT)) bit description
All information provided in this document is subject to legal disclaimers.
Pin interrupt status. Bit n returns the status, clears the edge
interrupt, or inverts the active level of the pin selected in
PINTSELn.
Read 0: interrupt is not being requested for this interrupt pin.
Write 0: no operation.
Read 1: interrupt is being requested for this interrupt pin.
Write 1 (edge-sensitive): clear rising- and falling-edge
detection for this pin.
Write 1 (level-sensitive): switch the active level for this pin (in
the PINTENT_F register).
Reserved.
Value
0
1
0
1
0
1
-
Rev. 00.13 — 20 July 2011
Description
Group interrupt status. This bit is cleared by writing a
one to it. Writing zero has no effect.
No interrupt request is pending.
Interrupt request is active.
Combine enabled inputs for group interrupt
OR functionality: A grouped interrupt is generated
when any one of the enabled inputs is active (based
on its programmed polarity).
AND functionality: An interrupt is generated when all
enabled bits are active (based on their programmed
polarity).
Group interrupt trigger
Edge-triggered
Level-triggered
Reserved
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
Reset value
0
0
0
0
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