LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 267

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
16.6 Register description
Table 196. Register overview: GPDMA (base address 0x4000 2000)
<Document ID>
User manual
Name
General registers
INTSTAT
INTTCSTAT
INTTCCLEAR
INTERRSTAT
INTERRCLR
RAWINTTCSTAT
RAWINTERRSTAT
ENBLDCHNS
SOFTBREQ
SOFTSREQ
SOFTLBREQ
SOFTLSREQ
CONFIG
SYNC
Channel 0 registers
C0SRCADDR
C0DESTADDR
C0LLI
C0CONTROL
C0CONFIG
Channel 1 registers
C1SRCADDR
C1DESTADDR
C1LLI
C1CONTROL
C1CONFIG
Channel 2 registers
C2SRCADDR
C2DESTADDR
C2LLI
C2CONTROL
C2CONFIG
The DMA Controller supports 8 channels. Each channel has registers specific to the
operation of that channel. Other registers controls aspects of how source peripherals
relate to the DMA Controller. There are also global DMA control and status registers.
Access Address
RO
RO
WO
RO
WO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x100
0x104
0x108
0x10C
0x110
0x120
0x124
0x128
0x12C
0x130
0x140
0x144
0x148
0x14C
0x150
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Description
DMA Interrupt Status Register
DMA Interrupt Terminal Count Request Status
Register
DMA Interrupt Terminal Count Request Clear
Register
DMA Interrupt Error Status Register
DMA Interrupt Error Clear Register
Register
DMA Raw Error Interrupt Status Register
DMA Enabled Channel Register
DMA Software Burst Request Register
DMA Software Single Request Register
DMA Software Last Burst Request Register
DMA Software Last Single Request Register
DMA Configuration Register
DMA Synchronization Register
DMA Channel 0 Source Address Register
DMA Channel 0 Destination Address Register
DMA Channel 0 Linked List Item Register
DMA Channel 0 Control Register
DMA Channel 0 Configuration Register
DMA Channel 1 Source Address Register
DMA Channel 1 Destination Address Register
DMA Channel 1 Linked List Item Register
DMA Channel 1 Control Register
DMA Channel 1 Configuration Register
DMA Channel 2 Source Address Register
DMA Channel 2 Destination Address Register
DMA Channel 2 Linked List Item Register
DMA Channel 2 Control Register
DMA Channel 2 Configuration Register
DMA Raw Interrupt Terminal Count Status
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
0x0000 0000
-
0x0000 0000
-
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
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