LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 292
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Fig 27. LLI example
0x2002 0000
0x2002 0010
0x2002 0020
0x2002 0070
16.8.5.1.2 Example of scatter/gather DMA
LLI1
LLI2
LLI3
LLI8
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
Source address
Destination address = peripheral
Next LLI address
Control information
See
peripheral. The addresses of each LLI entry are given, in hexadecimal, at the left-hand
side of the figure. The right side of the figure shows the memory containing the data to be
transferred.
The first LLI, stored at 0x2002 0000, defines the first block of data to be transferred, which
is the data stored from address 0x2002 A200 to 0x2002 ADFF:
The second LLI, stored at 0x2002 0010, describes the next block of data to be transferred:
5. An interrupt can be generated at the end of each LLI depending on the Terminal
•
•
•
•
•
•
•
•
Count bit in the CCONTROL Register. If this bit is set an interrupt is generated at the
end of the relevant LLI. The interrupt request must then be serviced and the relevant
bit in the INTTCCLEAR Register must be set to clear the interrupt.
Source start address 0x2002 A200.
Destination address set to the destination peripheral address.
Transfer width, word (32-bit).
Transfer size, 3072 bytes (0xC00).
Source and destination burst sizes, 16 transfers.
Next LLI address, 0x2002 0010.
Source start address 0x2002 B200.
Destination address set to the destination peripheral address.
Figure 27
Linked List Array
for an example of an LLI. A section of memory is to be transferred to a
All information provided in this document is subject to legal disclaimers.
= 0x 2002 A200
= 0x2002 0010
= length 3072
= 0x 2002 B200
= 0x2002 0020
= length 3072
= 0x 2002 C200
= 0x2002 0030
= length 3072
= 0x 2003 1200
= 0 (end of list)
= length 3072
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
0x2002 CDFF
0x2002 ADFF
0x2002 BDFF
0x2003 1DFF
0x2002 C200
0x2002 A200
0x2002 B200
0x2003 1200
3072 bytes of data
3072 bytes of data
3072 bytes of data
3072 bytes of data
UM10430
© NXP B.V. 2011. All rights reserved.
292 of 1164
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