LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 490

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 411. MAC VLAN tag register (MAC_VLAN_TAG, address 0x4001 01C) bit description
Table 412. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit description
<Document ID>
User manual
Bit
15:0
16
31:17
Bit
0
2:1
3
4
Symbol
VL
ETV
-
Symbol
RXIDLES
TAT
FIFOSTA
T0
-
RXFIFO
STAT1
22.6.8 MAC VLAN tag register
22.6.9 MAC Debug register
Description
VLAN Tag Identifier for Receive Frames
This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the
fifteenth and sixteenth bytes of the frames being received for VLAN frames.
Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and
bits[11:0] are the VLAN tag’s VLAN Identifier (VID) field. When the ETV bit is set, only
the VID (Bits[11:0]) is used for comparison.
If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and
sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field
value of 0x8100 to be VLAN frames.
Enable 12-Bit VLAN Tag Comparison
When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN
tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with
the corresponding field in the received VLAN-tagged frame.
When this bit is reset, all 16 bits of the received VLAN frame’s fifteenth and sixteenth
bytes are used for comparison.
Reserved
Description
When high, it indicates that the MAC MII receive protocol engine is actively receiving
data and not in IDLE state.
When high, it indicates the active state of the small FIFO Read and Write controllers
respectively of the MAC receive Frame Controller module.
Reserved
When high, it indicates that the MTL RxFIFO Write Controller is active and
transferring a received frame to the FIFO.
The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames.
The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with
0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, it
sets the received VLAN bit in the receive frame status. The legal length of the frame is
increased from 1518 bytes to 1522 bytes.
If the VLAN Tag register is configured to be double-synchronized to the MII clock domain,
then consecutive writes to these register should be performed only after at least 4 clock
cycles in the destination clock domain.
This debug register gives the status of all the main modules of the transmit and receive
data-paths and the FIFOs. An all-zero status indicates that the MAC core is in idle state
(and FIFOs are empty) and no activity is going on in the data-paths.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x000
0
0
0x000
0
Reset
value
490 of 1164
Access
R/W
R/W
RO
Access