LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 746
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
Table 689: Register overview: UART1 (base address 0x4008 2000)
Name
RS485ADRMA
TCH
RS485DLY
FIFOLVL
All information provided in this document is subject to legal disclaimers.
Access Address
R/W
R/W
RO
Rev. 00.13 — 20 July 2011
0x054
0x058
offset
0x050
Description
RS-485/EIA-485 address match. Contains the
address match value for RS-485/EIA-485 mode.
RS-485/EIA-485 direction control delay.
FIFO Level register. Provides the current fill
levels of the transmit and receive FIFOs.
Chapter 33: LPC18xx UART1
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
746 of 1164
Reset
value
0x00
0x00
0x00
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