LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 501

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 427. DMA Status register (DMA_STAT, address 0x4001 1014) bit description
<Document ID>
User manual
Bit
7
8
9
10
12:11
13
14
Symbol
RU
RPS
RWT
ETI
-
FBI
ERI
Description
Receive buffer unavailable
This bit indicates that the Next Descriptor in the Receive List is owned by the host and
cannot be acquired by the DMA. Receive Process is suspended. To resume
processing Receive descriptors, the host should change the ownership of the
descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is
issued, Receive Process resumes when the next recognized incoming frame is
received. This bit is set only when the previous Receive Descriptor was owned by the
DMA.
Received process stopped
This bit is asserted when the Receive Process enters the Stopped state.
Receive watchdog timeout
This bit is asserted when a frame with a length greater than 2,048 bytes is received
(10,240 when Jumbo Frame mode is enabled).
Early transmit interrupt
This bit indicates that the frame to be transmitted was fully transferred to the MTL
Transmit FIFO.
Reserved
Fatal bus error interrupt
This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is
set, the corresponding DMA engine disables all its bus accesses.
Early receive interrupt
This bit indicates that the DMA had filled the first data buffer of the packet. Receive
Interrupt bit 6 in this register automatically clears this bit.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
501 of 1164
Access
R/SS/
WC
R/SS/
WC
R/SS/
WC
R/SS/
WC
RO
R/SS/
WC
R/SS/
WC