LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 44
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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6.6.2 Edge configuration register
Table 19.
This register works in combination with the level configuration register HILO (see
Table
The EDGE configuration register determines whether the event router responds to a level
change (EDGEn=1), or a constant level (EDGEn=0). The HILOn bit determines a
response to a rising edge (HILOn=1) or a falling edge (HILOn=0).
Table 20.
Bit
13
14
15
16
18:17 -
19
31:20 -
HILOn
0
0
1
1
19) to configure the level or edge detection for each input to the event router.
Symbol
TIM2_L
TIM6_L
QEI_L
TIM14_L
RESET_L
Level configuration register (HILO - address 0x4004 4000) bit description
EDGE and HILO combined register settings
All information provided in this document is subject to legal disclaimers.
EDGEn
0
1
0
1
Value Description
0
1
0
1
0
1
0
1
-
0
1
-
Rev. 00.13 — 20 July 2011
Level detect mode for combined timer output 2 event.
Detect LOW level if bit 13 in the EDGE register is 0. Detect
falling edge if bit 13 in the EDGE register is 1.
Detect HIGH level if bit 13 in the EDGE register is 0.
Detect rising edge if bit 13 in the EDGE register is 1.
Level detect mode for combined timer output 6 event.
Detect LOW level if bit 14 in the EDGE register is 0. Detect
falling edge if bit 14 in the EDGE register is 1.
Detect HIGH level if bit 14 in the EDGE register is 0.
Detect rising edge if bit 14 in the EDGE register is 1.
Level detect mode for QEI event.
Detect LOW level if bit 15 in the EDGE register is 0. Detect
falling edge if bit 15 in the EDGE register is 1.
Detect HIGH level if bit 15 in the EDGE register is 0.
Detect rising edge if bit 15 in the EDGE register is 1.
Level detect mode for combined timer output 14 event.
Detect LOW level if bit 16 in the EDGE register is 0. Detect
falling edge if bit 16 in the EDGE register is 1.
Detect HIGH level if bit 16 in the EDGE register is 0.
Detect rising edge if bit 16 in the EDGE register is 1.
Reserved.
.
Detect LOW level if bit 17 in the EDGE register is 0. Detect
falling edge if bit 17 in the EDGE register is 1.
Detect HIGH level if bit 17 in the EDGE register is 0.
Detect rising edge if bit 17 in the EDGE register is 1.
Reserved.
Description
Detect LOW level
Detect falling edge
Detect HIGH level
Detect rising edge
Chapter 6: LPC18xx Event router
UM10430
© NXP B.V. 2011. All rights reserved.
44 of 1164
Reset
value
0
0
0
0
0
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