LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 798

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 743. I2S Receive Mode Control register (RXMODE - address 0x400A 2034 (I2S0) and 0x400A 3034 (I2S1)) bit
35.7 Functional description
<Document ID>
User manual
Bit
2
3
31:4
Symbol
RX4PIN
RXMCENA
-
description
35.7.1 I
Value Description
The I2S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio
information. Some details of I2S implementation are:
When switching between data width or modes the I2S must be reset via the reset bit in the
control register in order to ensure correct synchronization. It is advisable to set the stop bit
also until sufficient data has been written in the transmit FIFO. Note that when stopped
data output is muted.
All data accesses to FIFOs are 32 bits.
A data sample in the FIFO consists of:
2
•
•
•
•
•
•
•
•
•
S transmit and receive interfaces
Receive 4-pin mode selection. When 1, enables 4-pin mode.
Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1,
output of RX_MCLK is enabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When the FIFO is empty, the transmit channel will repeat transmitting the same data
until new data is written to the FIFO.
When mute is true, the data value 0 is transmitted.
When mono is false, two successive data words are respectively left and right data.
Data word length is determined by the wordwidth value in the configuration register.
There is a separate wordwidth value for the receive channel and the transmit channel.
– 0: word is considered to contain four 8-bit data words.
– 1: word is considered to contain two 16-bit data words.
– 3: word is considered to contain one 32-bit data word.
When the transmit FIFO contains insufficient data the transmit channel will repeat
transmitting the last data until new data is available. This can occur when the
microprocessor or the DMA at some time is unable to provide new data fast enough.
Because of this delay in new data there is a need to fill the gap, which is
accomplished by continuing to transmit the last sample. The data is not muted as this
would produce an noticeable and undesirable effect in the sound.
The transmit channel and the receive channel only handle 32-bit aligned words, data
chunks must be clipped or extended to a multiple of 32 bits.
1´32 bits in 8-bit or 16-bit stereo modes.
1´32 bits in mono modes.
2´32 bits, first left data, second right data, in 32-bit stereo modes.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Figure 122
shows the possible data sequences.
Chapter 35: LPC18xx I2S interface
UM10430
© NXP B.V. 2011. All rights reserved.
798 of 1164
Reset
value
0
0
NA