LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 32
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
Fig 15. Boot process timing
processor status
3.3.6 ISP
VDDREG
RESET
IRC12
GND
In-System programming (ISP) is programming or re-programming the on-chip SRAM
memory, using the boot loader software and the USART0 serial port. This can be done
when the part resides in the end-user board. ISP allows to load data into on-chip SRAM
and execute code from on-chip SRAM. For details, see
ramp up
supply
All information provided in this document is subject to legal disclaimers.
IRC12
starts
valid
threshold
22 µs
Rev. 00.13 — 20 July 2011
IRC12
stable
check boot
selection
t
0.5µs; IRC stability count
a
pins
µs
initialise
t
b
device
boot time
µs
copy image to
Chapter
Chapter 3: LPC18xx Boot ROM
embedded
t
c
µs
SRAM
40.
user code
UM10430
© NXP B.V. 2011. All rights reserved.
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