LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 574
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
23.7.5.6 Cursor image format
The LCD frame buffer supports three packing formats, but the hardware cursor image
requirement has been simplified to support only LBBP. This is little-endian byte,
big-endian pixel for Windows CE mode.
The Image RAM start address is offset by 0x800 from the LCD base address, as shown in
the register description in this chapter.
The displayed cursor coordinate system is expressed in terms of (X,Y). 64 x 64 is an
extension of the 32 x 32 format shown in
32 by 32 pixel format
Four cursors are held in memory, each with the same pixel format.
base addresses for the four cursors.
Table 489. Addresses for 32 x 32 cursors
Address
0x4000 8800
0x4000 8900
0x4000 8A00
0x4000 8B00
Fig 56. Cursor image format
LEFT
All information provided in this document is subject to legal disclaimers.
(0, 29)
(0, 30)
(0, 31)
(0, 0)
(0, 1)
(0, 2)
Rev. 00.13 — 20 July 2011
(1, 29)
(1, 30)
(1, 31)
(1, 0)
(1, 1)
(1, 2)
Description
Cursor 0 start address.
Cursor 1 start address.
Cursor 2 start address.
Cursor 3 start address.
(2, 29)
(2, 30)
(2, 31)
(2, 0)
(2, 1)
(2, 2)
BOTTOM
Figure
TOP
56.
(29, 29)
(29, 30)
(29, 31)
(29, 0)
(29, 1)
(29, 2)
(30, 29)
(30, 30)
(30, 31)
(30, 0)
(30, 1)
(30, 2)
Chapter 23: LPC18xx LCD
(31, 29)
(31, 30)
(31, 31)
(31, 0)
(31, 1)
(31, 2)
Table 489
UM10430
© NXP B.V. 2011. All rights reserved.
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