LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 799

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 744. I2S transmit modes
<Document ID>
User manual
DAO bit
5
0
0
0
0
TXMODE
bits [3:0]
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
35.7.2 I
Data is read from the transmit FIFO after the falling edge of WS, it will be transferred to
the transmit clock domain after the rising edge of WS. On the next falling edge of WS the
left data will be loaded in the shift register and transmitted and on the following rising edge
of WS the right data is loaded and transmitted.
The receive channel will start receiving data after a change of WS. When word select
becomes low it expects this data to be left data, when WS is high received data is
expected to be right data. Reception will stop when the bit counter has reached the limit
set by wordwidth. On the next change of WS the received data will be stored in the
appropriate hold register. When complete data is available it will be written into the receive
FIFO.
The clocking and WS usage of the I2S interface is configurable. In addition to master and
slave modes, which are independently configurable for the transmitter and the receiver,
several different clock sources are possible, including variations that share the clock
and/or WS between the transmitter and receiver. This last option allows using I2S with
fewer pins, typically four.
Many configurations are possible that are not considered useful, the following tables and
figures give details of the configurations that are most likely to be useful.
Description
Typical transmitter master mode. See
The I2S transmit function operates as a master.
The transmit clock source is the fractional rate divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.
Transmitter master mode sharing the receiver reference clock. See
The I2S transmit function operates as a master.
The transmit clock source is RX_REF.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.
4-wire transmitter master mode sharing the receiver bit clock and WS. See
The I2S transmit function operates as a master.
The transmit clock source is the RX bit clock.
The WS used is the internally generated RX_WS.
The TX_MCLK pin is not enabled for output.
Transmitter master mode with TX_MCLK output. See
The I2S transmit function operates as a master.
The transmit clock source is the fractional rate divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is enabled for output.
2
S operating modes
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Figure
110.
Figure
Chapter 35: LPC18xx I2S interface
110.
Figure
111.
Figure
UM10430
© NXP B.V. 2011. All rights reserved.
112.
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