LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 269

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
16.6.2 DMA Interrupt Terminal Count Request Status Register
16.6.3 DMA Interrupt Terminal Count Request Clear Register
16.6.4 DMA Interrupt Error Status Register
Table 197. DMA Interrupt Status register (INTSTAT, address 0x4000 2000) bit description
The INTTCSTAT Register is read-only and indicates the status of the terminal count after
masking.
Table 198. DMA Interrupt Terminal Count Request Status Register (INTTCSTAT, address
The INTTCCLEAR Register is write-only and clears one or more terminal count interrupt
requests. When writing to this register, each data bit that is set HIGH causes the
corresponding bit in the status register (IntTCStat) to be cleared. Data bits that are LOW
have no effect.
Table 199. DMA Interrupt Terminal Count Request Clear Register (INTTCCLEAR, address
The INTERRSTAT Register is read-only and indicates the status of the error request after
masking.
Bit
7:0
31:8 -
Bit
7:0
31:8 -
Bit
7:0
31:8
Symbol
INTSTAT
Symbol
INTTCSTAT
Symbol
INTTCCLEAR Allows clearing the Terminal count interrupt request
-
0x4000 2004) bit description
0x4000 2008) bit description
All information provided in this document is subject to legal disclaimers.
Description
Status of DMA channel interrupts after masking. Each bit
represents one channel:
0 - the corresponding channel has no active interrupt
request.
1 - the corresponding channel does have an active interrupt
request.
Reserved. Read undefined.
Description
Terminal count interrupt request status for DMA
channels. Each bit represents one channel:
0 - the corresponding channel has no active terminal
count interrupt request.
1 - the corresponding channel does have an active
terminal count interrupt request.
Reserved. Read undefined.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Description
(IntTCStat) for DMA channels. Each bit represents one
channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel terminal count
interrupt.
Reserved. Read undefined. Write reserved bits as
zero.
Rev. 00.13 — 20 July 2011
UM10430
© NXP B.V. 2011. All rights reserved.
-
Reset
value
0x00
Reset
value
0x00
-
Reset
value
0x00
-
269 of 1164
Access
RO
-
Access
WO
-
Access
RO
-