r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1056

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 23 Gigabit Ethernet Controller (GETHER)
(2)
The program accesses MII registers via PIR. Access is implemented by a combination of 1-bit-unit
data write, 1-bit-unit data read, bus release, and independent bus release. Figure 23.33 shows the
MII register access timing. The timing will differ depending on the PHY-LSI type.
Rev. 1.00 Oct. 01, 2007 Page 990 of 1956
REJ09B0256-0100
MII Register Access Procedure
(1)
(2)
(3)
Figure 23.34 Bus Release Flowchart (TA in Read in Figure 23.33)
(1)
(2)
(3)
Write to PHY interface
register
ET_MMD = 1
ET_MDO = write data
ET_MDC = 0
Write to PHY interface
register
ET_MMD = 1
ET_MDO = write data
ET_MDC = 1
Write to PHY interface
register
ET_MMD = 1
ET_MDO = write data
ET_MDC = 0
Write to PHY interface
register
ET_MMD = 0
ET_MDC = 0
Write to PHY interface
register
ET_MMD = 0
ET_MDC = 1
Write to PHY interface
register
ET_MMD = 0
ET_MDC = 1
Figure 23.33 1-Bit Data Write Flowchart
ET_MDC
ET_MDO
ET_MDC
ET_MDO
1-bit data write timing
relationship
(1) (2)
Bus release timing
relationship
(1) (2)
(3)
(3)

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