r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1169

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

In serial reception, the SCIF operates as described below.

1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal

2. The received data is stored in SCRSR in LSB-to-MSB order.

3. The parity bit and stop bit are received.

4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-

Figure 27.13 shows an example of the operation for reception in asynchronous mode.

synchronization and starts reception.

After receiving these bits, the SCIF carries out the following checks.

(a) Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only

(b) The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.*

(d) Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not

data-full interrupt (RXI) request is generated.

If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error

interrupt (ERI) request is generated.

If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a

break reception interrupt (BRI) request is generated.

Note: * Reception continues even when a parity error or framing error occurs.

the first is checked.

error has occurred.*

If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR.

(Example with 8-Bit Data, Parity, One Stop Bit)

Figure 27.13 Sample SCIF Receive Operation

RXI interrupt

Section 27 Serial Communication Interface with FIFO (SCIF)

Data read and RDF flag

read as 1 then cleared to

0 by RXI interrupt handler

Rev. 1.00 Oct. 01, 2007 Page 1103 of 1956

ERI interrupt request

generated by receive

REJ09B0256-0100