r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 883

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.3.5
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI internal
registers via the GMII/MII/RMII.
Bit
31 to 4
3
2
1
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
PHY Interface Register (PIR)
Bit Name

MDI
MDO
MMD
MDC
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
Undefined
0
0
0
28
12


R
R
0
0
27
11
R/W
R
R
R/W
R/W
R/W


R
R
0
0
26
10


R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
GMII/MII/RMII Management Data-In
Indicates the level of the ET_MDIO pin.
GMII/MII/RMII Management Data-Out
Outputs the value set in this bit from the ET_MDIO pin
when the MMD bit is 1.
GMII/MII/RMII Management Mode
Specifies the data read/write direction with respect to
the GMII/MII/RMII.
0: Read direction is specified
1: Write direction is specified
GMII/MII/RMII Management Data Clock
Outputs the value set in this bit from the ET_MDC pin
and supplies the GMII/MII/RMII with the management
data clock. For the method of accessing the
GMII/MII/RMII registers, see section 23.5.4, Accessing
MII Registers.
25


R
R
0
9
0
24


R
R
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
23


R
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 817 of 1956
22


R
R
0
6
0
21


R
R
0
5
0
20


R
R
0
4
0
MDI
19


R
R
0
3
MDO
REJ09B0256-0100
R/W
18

R
0
2
0
MMD
17

R
0
1
0
MDC
R/W
16

R
0
0
0