r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1629

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

• Data Stage (Control-Out)

The application first analyzes command data from the host in the setup stage, and determines the

subsequent data stage direction. If the result of command data analysis is that the data stage is out-

transfer, the application waits for data from the host, and after data is received (IFR0/EP0o TS =

1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties

the receive FIFO, and waits for reception of the next data.

The end of the data stage is identified when the host transmits an IN token and the status stage is

Data reception from host

OUT token reception

(IFR0/EP0o TS = 1)

Set EP0o reception

USB function

complete flag

Figure 36.7 Data Stage (Control-Out) Operation

Interrupt request

Section 36 USB Function Controller (USBF)

Rev. 1.00 Oct. 01, 2007 Page 1563 of 1956

receive data size register

data register (EPDR0o)

(TRG/EP0o RDFN = 1)

Read data from EP0o

Clear EP0o reception

Write 1 to EP0o read

(IFR0/EP0o TS = 0)

complete flag

complete bit

REJ09B0256-0100