r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1477

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

33.5.2
The HAC transmitter outputs serial audio data on the HAC_SDOUT pin, synchronous to The
The transmitter supports data only in slots 1 to 4. The TX buffer holds data that has been
transferred using PIO or DMA, and sets the corresponding status bit. It is possible to write 20-bit
data within a 32-bit register using PIO.
In the case of a TX underrun, the HAC will transmit the current TX buffer data until the next data
arrives.
33.5.3
The HAC supports DMA transfer for slots 3 and 4 of both the RX and TX frames. Specify the slot
data size for DMA transfer, 16 or 20 bits, with the DMARX16 and DMATX16 bits in HACACR.
When the data size is 20 bits, transfer of data slots 3 and 4 requires two local bus access cycles.
Since each of the receiver and transmitter has its DMA request, the stereo mode generates a DMA
request for slots 3 and 4 separately. The mono mode generates a DMA request for just one slot.
When the data size is 16 bits, data from slots 3 and 4 are packed into a single 32-bit quantity (left
data and right data are in PCML), which requires only one local bus access cycle.
It may be necessary to halt a DMA transfer before the end count is reached, depending on system
applications. If so, clear the corresponding DMA bit in HACACR to 0 (DMA disabled). To
resume a DMA transfer, reprogram the DMAC and then set the corresponding DMA bit to 1
(DMA enabled).
33.5.4
Interrupts can be used for flag events from the receiver and transmitter. Make the setting for each
interrupt in the corresponding interrupt enable register. Interrupts include a request to the CPU to
read/write slot data, overrun and underrun. To get the interrupt source, read the status register.
Writing 0 to the bit will clear the corresponding interrupt.
transmitter sets the tag bits in slot 0 to indicate which slots in the current frame contain valid data.
It loads data slots to the current TX frame in response to the corresponding slot request bits from
the previous RX frame.
Transmitter
DMA
Interrupts
Rev. 1.00 Oct. 01, 2007 Page 1411 of 1956
Section 33 Audio Codec Interface (HAC)
REJ09B0256-0100