r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1183

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Thus, the reception margin in asynchronous mode is given by formula (1).

M: Receive margin (%)

N: Ratio of bit rate to clock (N = 16)

D: Clock duty (D = 0 to 1.0)

From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2).

When D = 0.5 and F = 0:

However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to

When using an external clock as the synchronization clock, after SCFTDR is updated by the

DMAC, an external clock should be input after at least five peripheral clock (Pck) cycles. A

malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR

(see figure 27.23).

Frame length (L = 9 to 12)

Absolute value of clock rate deviation

When Using the DMAC

M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ............................................... (2)

Figure 27.23 Example of Synchronization Clock Transfer by DMAC

Note: When the SCIF is operated on an external clock, set t > 4.

) - (L - 0.5) F -

Section 27 Serial Communication Interface with FIFO (SCIF)

(1 + F) × 100 % .................. (1)

Rev. 1.00 Oct. 01, 2007 Page 1117 of 1956

REJ09B0256-0100