r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1175

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

(5)
Figure 27.19 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When switching the operating mode from asynchronous mode to clocked synchronous mode
without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags
are cleared to 0.
Serial Data Reception (Clocked Synchronous Mode)
No
No
Clear RE bit in SCSCR to 0
Read ORER flag in SCLSR
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Figure 27.19 Sample Serial Reception Flowchart (1)
Read receive data in
flag in SCFSR to 0
All data received?
Start of reception
End of reception
Initialization
ORER = 1?
RDF = 1?
No
Yes
Yes
Error handling
Section 27 Serial Communication Interface with FIFO (SCIF)
[1]
[3]
[4]
Yes
[2]
[1] SCIF initialization:
[2] Receive error handling:
[3] SCIF status check and receive data
[4] Serial reception continuation
Rev. 1.00 Oct. 01, 2007 Page 1109 of 1956
See Sample SCIF Initialization
Flowchart in figure 27.16.
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be
resumed while the ORER flag is set
to 1.
read:
Read SCFSR and check that RDF =
1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
0 to 1 can also be identified by an
RXI interrupt.
procedure:
To continue serial reception, read at
least the receive trigger set number
of receive data bytes from SCFRDR,
read 1 from the RDF flag, then clear
the RDF flag to 0. The number of
receive data bytes in SCFRDR can
be ascertained by reading SCFRDR.
REJ09B0256-0100