r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 327

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
23
22
21
20
19
18
17
16
15
14
13
12
Bit Name
IC007
IC006
IC005
IC004
IC003
IC002
IC001
—
IC115
IC114
IC113
IC112
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Clears masking of an
interrupt request when
IRL[3:0] = HLLL (H'8).
Clears masking of an
interrupt request when
IRL[3:0] = HLLH (H'9).
Clears masking of an
interrupt request when
IRL[3:0] = HLHL (H'A).
Clears masking of an
interrupt request when
IRL[3:0] = HLHH (H'B).
Clears masking of an
interrupt request when
IRL[3:0] = HHLL (H'C).
Clears masking of an
interrupt request when
IRL[3:0] = HHLH (H'D).
Clears masking of an
interrupt request when
IRL[3:0] = HHHL (H'E).
Reserved
This bit is always read as 0. The write value should
always be 0.
Clears masking of an
interrupt request when
IRL[7:4] = LLLL (H'0).
Clears masking of an
interrupt request when
IRL[7:4] = LLLH (H'1).
Clears masking of an
interrupt request when
IRL[7:4] = LLHL (H'2).
Clears masking of an
interrupt request when
IRL[7:4] = LLHH (H'3).
Rev. 1.00 Oct. 01, 2007 Page 261 of 1956
Section 9 Interrupt Controller (INTC)
[When reading]
An undefined value is
read.
[When writing]
0: Invalid
1: Clears the
[When reading]
An undefined value is
read.
[When writing]
0: Invalid
1: Clears the
corresponding interrupt
mask (Interrupts are
enabled)
corresponding interrupt
mask (Interrupts are
enabled)
REJ09B0256-0100