r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1594

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 36 USB Function Controller (USBF)

36.3.19 EP1 Data Register (EPDR1)

EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,

and has a capacity of twice the maximum packet size. The number of receive byte is displayed in

the EP1 receive data size register. The buffer on read side can be received again by writing

EP1RDFN in the trigger register to 1 after data is read. The receive data of this FIFO buffer can be

transferred by DMA. This FIFO buffer can be initialized by means of EP1CLR in the FCLR0

Rev. 1.00 Oct. 01, 2007 Page 1528 of 1956

REJ09B0256-0100

Initial value:

Initial Value R/W Description

Data register for endpoint1 transfer

These bits are always read as undefined value.