r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1374

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 31 Multimedia Card Interface (MMCIF)
31.3.11 Card Status Register (CSTR)
CSTR indicates the MMCIF status during command sequence execution.
Rev. 1.00 Oct. 01, 2007 Page 1308 of 1956
REJ09B0256-0100
Bit
7
6
5
Bit Name
BUSY
FIFO_FULL 0
FIFO_EMPTY
Initial value:
Initial
Value
0
0
R/W:
Bit:
BUSY
R
7
0
R/W
R
R
R
FIFO_
FULL
R
6
0
Description
Command Busy
Indicates command execution status. When the
CMDOFF bit in OPCR is set to 1, this bit is cleared to 0
because the MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state.
1: Command sequence execution in progress.
FIFO Full
This bit is set to 1 when the FIFO becomes full while
data is being received, and cleared to 0 when
RD_CONTI is set to 1 or the command sequence is
completed.
0: The FIFO is empty.
1: The FIFO is full.
FIFO Empty
This bit is set to 1 when the FIFO becomes empty while
data is being sent, and cleared to 0 when DATAEN is
set to 1 or the command sequence is completed.
Indicates whether the FIFO holds data or not.
0: The FIFO includes data.
1: The FIFO is empty.
EMPTY
FIFO_
R
5
0
CWRE
R
4
0
DTBUSY
R
3
0
DTBUSY_
—
TU
R
2
—
R
1
0
REQ
R
0
0