r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 490

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 1.00 Oct. 01, 2007 Page 424 of 1956
REJ09B0256-0100
Bit
17, 16
15 to 13 SRFC
12
11
Bit Name
RW
SWR
SRRD
Initial
Value
00
000
0
0
R/W
R/W
R/W
R/W
R/W
Description
Minimum Number of Cycles from Read command to
Write Commands
These bits specify the minimum number of cycles for
the WRITE command issuance after the READ
command is issued for the DDR-SDRAM.
00: 3 cycles
01: 4 cycles
10: 5 cycles
11: 6 cycles
Number of Cycles in Same Bank
These bits specify the number of cycles in the same
bank for the following access times (Trfc).
(1) From auto refresh to ACT command issuance
(2) From auto refresh to auto refresh
000: 11 cycles
001: 12 cycles
010: 13 cycles
011: 14 cycles
100: 15 cycles
Other than above: Setting prohibited
PRE/PREALL Command Issuance Cycle
Specifies the number of cycles from the last postamble
to PRE/PREALL command issuance in a write cycle
(Twr).
0: 2 cycles
1: 3 cycles
ACT Command Issuance Cycle between Banks
Specifies the minimum number of cycles from ACT
command issuance to ACT command issuance
between different banks (Trrd).
0: 2 cycles
1: 3 cycles