r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1836

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 41 User Break Controller (UBC)
41.2.2
CRR0 and CRR1 are readable/writable 32-bit registers which specify the operation to be executed
when channels 0 and 1 satisfy the match condition, respectively. The following operations can be
set in the CRR0 and CRR1 registers: (1) breaking at a desired timing for the instruction fetch cycle
and (2) requesting a break.
• CRR0
Rev. 1.00 Oct. 01, 2007 Page 1770 of 1956
REJ09B0256-0100
Bit
31 to 14
13
12 to 2
1
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Match Operation Setting Registers 0 and 1 (CRR0 and CRR1)
Bit Name
—
—
—
PCB
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
1
Initial
Value
All 0
1
All 0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R
R
R/W
26
10
R
R
0
0
Description
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
PC Break Select
Specifies either before or after instruction execution as
the break timing for the instruction fetch cycle. This bit
is invalid for breaks other than the ones for the
instruction fetch cycle.
0: Sets the PC break before instruction execution.
1: Sets the PC break after instruction execution.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
7
0
0
22
R
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
18
R
R
0
2
0
PCB
R/W
17
R
0
1
0
R/W
BIE
16
R
0
0
0