r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 321

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
25
24
23
22
21
20
19
18
17
16
Bit Name
IM009
IM008
IM007
IM006
IM005
IM004
IM003
IM002
IM001
—
Initial
Value
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Sets masking of an
interrupt request when
IRL [3:0] = LHHL (H'6).
Sets masking of an
interrupt request when
IRL [3:0] = LHHH (H'7).
Sets masking of an
interrupt request when
IRL [3:0] = HLLL (H'8).
Sets masking of an
interrupt request when
IRL [3:0] = HLLH (H'9).
Sets masking of an
interrupt request when
IRL [3:0] = HLHL (H'A).
Sets masking of an
interrupt request when
IRL [3:0] = HLHH (H'B).
Sets masking of an
interrupt request when
IRL [3:0] = HHLL (H'C).
Sets masking of an
interrupt request when
IRL [3:0] = HHLH (H'D).
Sets masking of an
interrupt request when
IRL [3:0] = HHHL (H'E).
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 255 of 1956
Section 9 Interrupt Controller (INTC)
[When reading]
0: Interrupts are accepted
1: Interrupts are masked
[When writing]
0: Invalid
1: Interrupts are masked
Initial value: 0
REJ09B0256-0100