r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 62

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Table 28.1
Table 28.2
Table 28.3
Table 28.4
Table 28.5
Table 28.6
Table 28.7
Table 28.8
Table 28.9
Section 29 Serial I/O with FIFO (SIOF)
Table 29.1
Table 29.2
Table 29.3
Table 29.4
Table 29.5
Table 29.6
Table 29.7
Table 29.8
Table 29.9
Table 29.10
Table 29.11
Table 29.12
Table 29.13
Table 29.14
Section 30 SIM Card Module (SIM)
Table 30.1
Table 30.2
Table 30.3
Table 30.4
Table 30.5
Table 30.6
Section 31 Multimedia Card Interface (MMCIF)
Table 31.1
Table 31.2
Table 31.3
Table 31.4
Table 31.5
Rev. 1.00 Oct. 01, 2007 Page lxii of lxvi
Pin Configuration................................................................................................ 1109
Register Configuration........................................................................................ 1110
Register States in each Operation Mode ............................................................. 1111
SCSMR Settings ................................................................................................. 1127
Baud Rate (3.6864 MHz Clock) ......................................................................... 1134
SCSMR Settings for Serial Transfer Format Selection....................................... 1138
SCSMR and SCSCR Settings for SCIF Clock Source Selection........................ 1139
Serial Transfer Formats (Asynchronous Mode).................................................. 1142
SCIF Interrupt Sources ....................................................................................... 1161
Pin Configuration................................................................................................ 1173
Register Configuration........................................................................................ 1174
Register State in Each Operating Mode.............................................................. 1176
Operation in Each Transfer Mode....................................................................... 1180
SIOF Serial Clock Frequency ............................................................................. 1204
Serial Transfer Modes......................................................................................... 1207
Frame Length...................................................................................................... 1207
Audio Mode Specification for Transmit Data..................................................... 1209
Audio Mode Specification for Receive Data ...................................................... 1210
Pin Configuration................................................................................................ 1229
Register Configuration........................................................................................ 1230
Register State in Each Operating Mode.............................................................. 1231
Register Settings for Smart Card Interface ......................................................... 1254
Example of Bit Rates (bits/s) for SCBRR Settings
(Pck0 = 66.6 MHz, SCSMPL = 371).................................................................. 1256
Interrupt Sources of Smart Card Interface .......................................................... 1262
Pin Configuration................................................................................................ 1273
Register Configuration........................................................................................ 1274
Register States in Each Processing Mode ........................................................... 1276
Correspondence between Commands and CMDTYR and RSPTYR Settings.... 1281
CMDR Configuration ......................................................................................... 1284
Setting Number of Channels in Control Data ................................................. 1211
Conditions to Issue Transmit Request ............................................................ 1214
Conditions to Issue Receive Request .............................................................. 1214
Transmit and Receive Reset ........................................................................... 1219
SIOF Interrupt Sources ................................................................................... 1220