r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 299

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt
requests to the CPU (SH-4A). The INTC has a register that sets the priority of each interrupt and
interrupt requests are processed according to the priority set in this register by the user.
9.1
SH-4 compatible specifications
• Fifteen levels of external interrupt priority can be set
• NMI noise canceller function
• NMI request masking when the block bit (BL) in the status register (SR) is set to 1
Extended function for SH-4A
• Automatically updates the IMASK bit in SR according to the accepted interrupt level
• Thirteen levels of on-chip module interrupt priority can be set
• User-mode interrupt disabling function
Figure 9.1 shows a block diagram of the INTC.
By setting the interrupt priority registers, the priorities of external interrupts can be selected
from 15 levels for individual request sources.
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception handling routine, the pin state can be checked, enabling it to be used as a noise
canceller.
Whether to mask NMI requests when the BL bit in SR is set to 1 can be selected.
By setting thirteen interrupt priority registers, the priorities of on-chip module interrupts can be
selected from 30 levels for individual request sources.
Specifying an interrupt mask level in the user interrupt mask level register (USERIMASK)
disables interrupts which are not higher in priority than the specified mask level in user mode.
Features
Section 9 Interrupt Controller (INTC)
Rev. 1.00 Oct. 01, 2007 Page 233 of 1956
Section 9 Interrupt Controller (INTC)
REJ09B0256-0100