r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1138

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 27 Serial Communication Interface with FIFO (SCIF)
Note: Pck0 = Peripheral Clock0
Rev. 1.00 Oct. 01, 2007 Page 1072 of 1956
REJ09B0256-0100
Bit
3
2
1
0
Bit Name
STOP
—
CKS1
CKS0
0
Initial
Value
0
0
0
R/W
R/W
R
R/W
R/W
Description
Stop Bit Length
In asynchronous mode, selects 1 or 2 bits as the stop
bit length. The stop bit setting is valid only in
asynchronous mode. Since the stop bit is not added in
clocked synchronous mode, the STOP bit setting is
invalid.
0: 1 stop bit*
1: 2 stop bits*
In reception, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit; if it is 0, it is treated as
the start bit of the next transmit character.
Note: 1. In transmission, a single 1-bit (stop bit) is
Reserved
This bit is always read as 0. The write value should
always be 0.
Clock Select 1 and 0
These bits select the clock source for the on-chip baud
rate generator. The clock source can be selected from
Pck0, Pck0/4, Pck0/16, and Pck0/64, according to the
setting of bits CKS1 and CKS0.
For details of the relationship between clock sources,
bit rate register settings, and baud rate, see section
27.3.8, Bit Rate Register (SCBRR).
00: Pck0 clock
01: Pck0/4 clock
10: Pck0/16 clock
11: Pck0/64 clock
2. In transmission, two 1-bits (stop bits) are
added to the end of a transmit character
before it is sent.
added to the end of a transmit character
before it is sent.
1
2