r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 431

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS6 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS6WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
For the PCMCIA interface, the setup time of addresses to the read/write strobe signals (CE1B/CS6
and CE2B) can be specified within a range from 0 to 15 cycles by bits TEDA[2:0], TEDB[2:0],
TEHA[2:0], and TEHB[2:0] in CS6PCR. In addition, the number of wait cycles can be specified
within a range from 0 to 50 cycles by bits PCWA[1:0] and PCWB[1:0]. The number of wait
cycles specified by CS6PCR is added to the value specified by IW[3:0] in CS6WCR or PCIW[3:0]
in CS6PCR.
11.5.3
SRAM interface
(1)
Basic Timing
The strobe signals for the SRAM interface of this LSI are output primarily based on the SRAM
connection. Figure 11.4 shows the basic timing of the SRAM interface. A no-wait normal access
is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus
cycle. The CSn signal is asserted at the rising edge of the clock in the T1 state, and negated at the
next rising edge of the clock in the T2 state. Therefore, there is no negation period in the case of
access at minimum pitch.
During reading, specification of an access size is not needed. The output of an access address on
the address pins (A25 to A0) is correct, however, since the access size is not specified, 32-bit data
is always output when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in
use. During writing, only the WE signal corresponding to the byte to be written is asserted. For
details, see section 11.5.1, Endian/Access Size and Data Alignment.
In 32-byte transfer, a total of 32 bytes are transferred continuously according to the bus width set.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wrap around method according to the set bus width. The bus is not
released during this transfer.
Rev. 1.00 Oct. 01, 2007 Page 365 of 1956
REJ09B0256-0100