r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1679

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
9
8
7 to 0
Bit Name
VSINTS
VEINTS

Initial Value
0
0
All 0
R/W
R/W
R/W
R
Description
Vsync Start Interrupt State
Indicates the LCDC's Vsync start interrupt handling
state. This bit is set to 1 at the time a Vsync start
interrupt is generated. During the Vsync start
interrupt handling routine, this bit should be cleared
by writing 0 to it.
0: LCDC did not generate a Vsync start interrupt or
1: LCDC has generated a Vsync start interrupt and
Vsync End Interrupt State
Indicates the LCDC's Vsync end interrupt handling
state. This bit is set to 1 at the time a Vsync end
interrupt is generated. During the Vsync end
interrupt handling routine, this bit should be cleared
by writing 0.
0: LCDC did not generate a Vsync end interrupt or
1: LCDC has generated a Vsync end interrupt and
Reserved
These bits are always read as 0. The write value
should always be 0.
has been informed that the generated Vsync start
interrupt has completed
has been informed that the generated Vsync end
interrupt has completed
has not yet been informed that the generated
Vsync start interrupt has completed
has not yet been informed that the generated
Vsync interrupt has completed
Rev. 1.00 Oct. 01, 2007 Page 1613 of 1956
Section 37 LCD Controller (LCDC)
REJ09B0256-0100