r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1578

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 36 USB Function Controller (USBF)
Rev. 1.00 Oct. 01, 2007 Page 1512 of 1956
REJ09B0256-0100
Bit
3
2
Bit Name
EP5 TR
EP5 TS
Initial Value
0
0
R/W Description
R/W EP5 (Isochronous-in) Transmit Request
R/W EP5 (Isochronous-in) Normal Transmission
Flag indicating the FIFO state of EP5.
After the SOF packet is received, the FIFO buffer is
switched automatically. The FIFO buffer which has
transmitted data to the host in the previous frame
(before SOF reception) can be written to by the CPU.
This bit indicates the transmit state in the previous
frame.
[Setting condition]
The FIFO buffer to be transmitted is empty when an IN
token is issued from the host to EP5.
[Clearing conditions]
Flag indicating the FIFO state of EP5.
After the SOF packet is received, the FIFO buffer is
switched automatically. The FIFO buffer which has
transmitted data to the host in the previous frame
(before SOF reception) can be written to by the CPU.
This bit indicates the transmit state in the previous
frame.
[Setting condition]
When a transmission was carried out normally in the
previous frame.
[Clearing conditions]
When reset
When 0 is written to by CPU
When reset
When 0 is written to by CPU

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