r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 21

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.3.4 E-MAC Interrupt Permission Register (ECSIPR)................................................. 816
23.3.5 PHY Interface Register (PIR) ............................................................................... 817
23.3.6 MAC Address High Register (MAHR) ................................................................ 818
23.3.7 MAC Address Low Register (MALR).................................................................. 819
23.3.8 Receive Frame Length Register (RFLR) .............................................................. 820
23.3.9 PHY Status Register (PSR)................................................................................... 821
23.3.10 PHY_INT Polarity Register (PIPR)...................................................................... 822
23.3.11 Transmit Retry Over Counter Register (TROCR) ................................................ 823
23.3.12 Delayed Collision Detect Counter Register (CDCR)............................................ 824
23.3.13 Lost Carrier Counter Register (LCCR)................................................................. 825
23.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 826
23.3.15 Frame Receive Error Counter Register (FRECR)................................................. 827
23.3.16 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 828
23.3.17 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 829
23.3.18 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 830
23.3.19 Carrier Extension Loss Counter Register (CERCR) ............................................. 831
23.3.20 Carrier Extension Error Counter Register (CEECR) ............................................ 832
23.3.21 Multicast Address Frame Receive Counter Register (MAFCR)........................... 833
23.3.22 Automatic PAUSE Frame Register (APR) ........................................................... 834
23.3.23 Manual PAUSE Frame Register (MPR) ............................................................... 835
23.3.24 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) .................... 836
23.3.25 PAUSE Frame Transmit Counter Register (PFTCR) ........................................... 837
23.3.26 PAUSE Frame Receive Counter Register (PFRCR)............................................. 838
23.3.27 GETHER Mode Register (GECMR) .................................................................... 839
23.3.28 Burst Cycle Count Upper-Limit Register (BCULR)............................................. 840
23.3.29 TSU Counter Reset Register (TSU_CTRST) ....................................................... 841
23.3.30 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) ............................................ 842
23.3.31 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) ............................................ 843
23.3.32 Relay FIFO Size Select Register (TSU_FCM) ..................................................... 844
23.3.33 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) ..................... 845
23.3.34 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) ..................... 847
23.3.35 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0)............ 849
23.3.36 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1)............ 851
23.3.37 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0)...................... 853
23.3.38 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1)...................... 855
23.3.39 Relay Function Set Register (Common) (TSU_FWSLC)..................................... 857
23.3.40 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAG0) ...................... 859
23.3.41 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAG1) ...................... 860
23.3.42 Relay Status Register (TSU_FWSR) .................................................................... 861
23.3.43 Relay Status Interrupt Mask Register (TSU_FWINMK)...................................... 864
Rev. 1.00 Oct. 01, 2007 Page xxi of lxvi