r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 476

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.1 shows a block diagram of the DDRIF.
• The SuperHyway bus interface (SHIF) is an interface between the CPU and SDRAM. The
• The LCDC interface (LCDIF) is an interface with the LCDC. The bus width is 32 bits and the
• The arbiter (ARBT) arbitrates SHIF that accesses the DDR-SDRAM and LCDIF requests
• The DDR-SDRAM controller (DDRC) controls read/write accesses to the DDR-SDRAM.
Rev. 1.00 Oct. 01, 2007 Page 410 of 1956
REJ09B0256-0100
SuperHyway bus protocol is used for interface. The bus width is 64 bits and the maximum
operating frequency is 133 MHz.
maximum operating frequency is 66 MHz.
among the requests from the abovementioned interfaces.
Commands are issued and read data is received according to the specified timing of the DDR-
SDRAM. Arbitration between the interfaces described above is performed with the priority
order determination defined separately. The I/O block that drives the DDR-SDRAM interface
signal and the register block related to the control of the DDR-SDRAM are included.
LCDC
SuperHyway bus
interface
interface
(LCDIF)
(SHIF)
LCDC
Figure 12.1 DDRIF Block Diagram
DDRIF
(ARBT)
Arbiter
From CPG
DDR-SDRAM
controller
(DDRC)
DLL
DDR
I/O
M_CLK0
M_CLK1
M_BKPRST
M_CKE
M_CS
M_RAS
M_CAS
M_WE
M_BA1, M_BA0
M_A13 to
M_A 0
M_DQM3 to
M_DQM0
M_DQS3 to
M_DQS0
M_D31 to
M_D0
M_VREF