r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 374

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Interrupt Controller (INTC)
9.6
Table 9.8 shows the interrupt response time, which is the interval from when an interrupt request
occurs until the interrupt exception handling is started and the start instruction of the exception
handling routine is fetched.
Table 9.8
[Legend]
Icyc: Period for one CPU clock cycle
Scyc: Period for one SHwy clock cycle
Bcyc: Period for one bus clock cycle
Pcyc: Period for one peripheral clock cycle (Pck0)
S: Number of instruction execution states
Note
Rev. 1.00 Oct. 01, 2007 Page 308 of 1956
REJ09B0256-0100
Item
Priority
determination time
Wait time until the
CPU finishes the
current sequence
Interval from when
interrupt exception
handling begins
(saving SR and PC)
until a SHwy bus
request is issued to
fetch the start
instruction of the
exception handling
routine
Response
time
*
Interrupt Response Time
Total
Minimum
In the case of Pcyc = Pck.
Interrupt Response Time
NMI
5Bcyc +
2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 5Bcyc
+ 2Pcyc
40Icyc
+ SxIcyc
IRL
8Bcyc +
2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 8Bcyc
+ 2Pcyc
52Icyc
+ SxIcyc
Number of States
IRQ
4Bcyc +
2Pcyc
S-1 (≥ 0)
× Icyc
11Icyc
+ 1Scyc
(S + 10) Icyc
+ 1Scyc
+ 4Bcyc
+ 2Pcyc
36Icyc
+ SxIcyc
Other than
GPIO/PCIC/
RTC
5Pcyc
(S + 10)
Icyc
+ 1Scyc
+ 5Pcyc
32Icyc
+ SxIcyc*
Peripheral Module
GPIO/PCIC/
RTC
7Pcyc
(S + 10)
Icyc
+ 1Scyc
+ 7Pcyc
40Icyc
+ SxIcyc*
Remarks
When
Icyc:Scyc:
Bcyc:Pcyc
= 4:2:1:1