r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 881

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

ET_PHY-INT Interrupt

Indicates the state of the ET_PHY-INT pin input from

the PHY-LSI.

0: ET_PHY-INT pin is not asserted

1: ET_PHY-INT pin is asserted

The signal polarity of the ET_PHY-INT pin can be set

Link Signal Change

Indicates that the ET_LNKSTA signal input from the

PHY-LSI has changed from high to low or low to high.

However, signal changes may be detected at the timing

at which the ET_LNKSTA function was selected using

PACR of the GPIO.

To check the current Link state, refer to the LMON bit in

the PHY status register (PSR).

0: Change in the ET_LNKSTA signal has not been

1: Change in the ET_LNKSTA signal has been

Magic Packet Detection

Indicates that a Magic Packet has been detected on the

0: Magic Packet has not been detected

1: Magic Packet has been detected

Illegal Carrier Detection

Indicates that the PHY-LSI has detected an illegal

carrier on the line. If a change in the signal input from

the PHY-LSI occurs in a period shorter than the

software recognition period, the correct information may

not be obtained. Refer to the timing specification for the

PHY-LSI used.

0: PHY-LSI has not detected an illegal carrier on the

1: PHY-LSI has detected an illegal carrier on the line

detected (high to low or low to high)

Section 23 Gigabit Ethernet Controller (GETHER)

Rev. 1.00 Oct. 01, 2007 Page 815 of 1956

REJ09B0256-0100