r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 42

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.1 DDRIF Block Diagram ........................................................................................... 410
Figure 12.2 Data Alignment in DDR-SDRAM and DDRIF....................................................... 414
Figure 12.3 Relationship between Write Values in SDMR and Output Signals to
Figure 12.4 DDR-SDRAM Access............................................................................................. 430
Figure 12.5 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes;
Figure 12.6 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes;
Figure 12.7 Basic DDRIF Timing
Figure 12.8 Basic DDRIF Timing
Figure 12.9 Basic DDRIF Timing (4 Burst Read: 32 Bytes; Without Auto-Precharge)............. 442
Figure 12.10 Basic DDRIF Timing (4 Burst Write: 32 Bytes; Without Auto-Precharge).......... 443
Figure 12.11 Basic DDRIF Timing
Figure 12.12 Basic DDRIF Timing (Mode Register Set (MRS)) ............................................... 445
Figure 12.13 Basic DDRIF Timing
Figure 12.14 Basic DDRIF Timing (Self-Refresh Entry from IDLE (REFS)/
Section 13 PCI Controller (PCIC)
Figure 13.1 PCIC Block Diagram .............................................................................................. 451
Figure 13.2 SuperHyway Bus to PCI Local Bus Access ............................................................ 530
Figure 13.3 SuperHyway Bus to PCI Local Bus Address Translation
Figure 13.4 SuperHyway Bus to PCI Local Bus Address Translation
Figure 13.5 SuperHyway Bus to PCI Local Bus Address Translation
Figure 13.6 SuperHyway Bus to PCI Local Bus Address Translation (PCI I/O) ....................... 533
Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Local bus
Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local bus
Figure 13.9 PCI local bus to SuperHyway bus Memory Map .................................................... 537
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Memory Pins ........................................................................................................... 428
Without Auto-Precharge) ........................................................................................ 438
Without Auto-Precharge) ........................................................................................ 439
(1 Burst Read: 1, 2, 4, or 8 Bytes; With Auto-Precharge)....................................... 440
(1 Burst Write: 1, 2, 4, or 8 Bytes; With Auto-Precharge)...................................... 441
(PCI Memory Space 0)............................................................................................ 531
(PCI Memory Space 1)............................................................................................ 532
(PCI Memory Space 2)............................................................................................ 532
(Non-Byte Swapping: TBS = 0).............................................................................. 535
(Byte Swapping: TBS = 1) ...................................................................................... 536
(Precharge all Banks (PREALL) to Bank Activate (ACT)).................................. 444
(Auto-Refresh (REFA) Enter/Exit to Bank Activate (ACT)) ............................... 446
Self-Refresh Exit (REFSX) to Any Command Input)........................................... 447