r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 145

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor.
Instruction execution is pipelined, and two instructions can be executed in parallel.
4.1
Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of seven stages: instruction
fetch (I1/I2), decode and register read (ID), execution (E1/E2/E3), and write-back (WB). An
instruction is executed as a combination of basic pipelines.
1. General Pipeline
2. General Load/Store Pipeline
3. Special Pipeline
4. Special Load/Store Pipeline
5. Floating-Point Pipeline
6.
Floating-Point Extended Pipeline
-Instruction fetch
-Instruction fetch
-Instruction fetch
-Instruction fetch
-Instruction fetch
-Instruction fetch
I1
I1
I1
I1
I1
I1
Pipelines
I2
I2
-Instruction
-Issue
decode
I2
I2
I2
I2
ID
-Instruction decode
-Issue
-Instruction decode
-Issue
-Register read
-Instruction decode
-Issue
-Register read
-Instruction decode
-Issue
-Register read
-Instruction decode
-Issue
-Register read
ID
-Register read
-Forwarding
Section 4 Pipelining
FE1
Figure 4.1 Basic Pipelines
ID
ID
ID
ID
-Register read
-Forwarding
-Operation
FS1
-Forwarding
-Address calculation
-Forwarding
FE2
E1
E1
E1
E1
-Operation
-Operation
FE3
FS2
-Operation
-Operation
-Memory data access
-Operation
-Operation
E2
E2
E2
E2
Rev. 1.00 Oct. 01, 2007 Page 79 of 1956
FE4
FS3
-Operation
FE5
-Operation
E3
E3
E3
E3
FS4
-Operation
FE6
Section 4 Pipelining
REJ09B0256-0100
-Write-back
-Write-back
-Write-back
-Operation
-Write-back
-Operation
-Write-back
WB
WB
WB
WB
FS
FS