r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1275

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

29.3.9
SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each
bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an
interrupt.
Initial value:
Bit
15
14
13
12
11
R/W:
BIt:
Interrupt Enable Register (SIIER)
Bit Name
TDMAE
TCRDYE
TFEMPE
TDREQE
RDMAE
R/W
MAE
15
TD
0
R/W
TCR
DYE
14
0
R/W
MPE
TFE
13
0
Initial
Value
0
0
0
0
0
R/W
TDR
EQE
12
0
MAE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RD
11
0
RDYE
R/W
RC
10
0
Description
Transmit Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The TDREQE bit can be set as
transmit interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty
Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer
1: Enables interrupts due to transmit data transfer
Receive Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The RDREQE bit can be set as
receive interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
FULE
R/W
requests
requests
RF
9
0
REQE
R/W
RD
8
0
R/W
—
7
0
Rev. 1.00 Oct. 01, 2007 Page 1209 of 1956
R/W
—
6
0
Section 29 Serial I/O with FIFO (SIOF)
ERRE
R/W
SA
5
0
ERRE
R/W
FS
4
0
OVFE
R/W
TF
3
0
REJ09B0256-0100
UDFE
R/W
TF
2
0
UDFE
R/W
RF
1
0
OVFE
R/W
RF
0
0