r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 420

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 354 of 1956
REJ09B0256-0100
Bit
14 to 12 TEDA
11
10 to 8
7
Bit Name

TEDB

Initial
Value
000
0
000
0
R/W
R/W
R
R/W
R
Description
OE/WE Assert Delay A
These bits set the delay time from address output to
OE/WE assertion for the access of first half area of
PCMCIA interface.
000: No wait cycle inserted
001: 1 wait cycle inserted
010: 2 wait cycles inserted
011: 3 wait cycles inserted
100: 6 wait cycles inserted
101: 9 wait cycles inserted
110: 12 wait cycles inserted
111: 15 wait cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
OE/WE Assert Delay B
These bits set the delay time from address output to
OE/WE assertion for the access of second half area of
PCMCIA interface.
000: No wait cycle inserted
001: 1 wait cycle inserted
010: 2 wait cycles inserted
011: 3 wait cycles inserted
100: 6 wait cycles inserted
101: 9 wait cycles inserted
110: 12 wait cycles inserted
111: 15 wait cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.