r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 187
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
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• Source: The access does not accord with the UTLB protection information (PR bits) shown
• Transition address: VBR + H'00000100
• Transition operations:
PR
00
01
10
11
Data_TLB_protection_violation_exception()
{
}
below.
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Data TLB Protection Violation Exception
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = read_access ? H'0000 00A0 : H'0000 00C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
Privileged Mode
Only read access possible
Read/write access possible
Only read access possible
Read/write access possible
User Mode
Access not possible
Access not possible
Only read access possible
Read/write access possible
Rev. 1.00 Oct. 01, 2007 Page 121 of 1956
Section 5 Exception Handling
REJ09B0256-0100
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