r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 266

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 7 Caches

5. Cache miss (copy-back, no write-back)

6. Cache miss (copy-back, with write-back)

7. Cache miss (write-through)

Rev. 1.00 Oct. 01, 2007 Page 200 of 1956

REJ09B0256-0100

A data write in accordance with the access size is performed for the data of the data field on

the hit way which is indexed by virtual address bits [4:0]. Then, the data, excluding the cache-

missed data which is written already, is read into the cache line on the way which is selected to

replace from the physical address space corresponding to the virtual address.

Data reading is performed, using the wraparound method, in order from the quad-word data (8

bytes) including the cache-missed data. While the remaining data on the cache line is being

read, the CPU can execute the next processing. When reading of one line of data is completed,

the tag corresponding to the physical address is recorded in the cache, 1 is written to the V bit

and the U bit on the way. Then the LRU bit is updated to indicate the way is latest one.

The tag and data field of the cache line on the way which is selected to replace are saved in the

write-back buffer. Then a data write in accordance with the access size is performed for the

data field on the hit way which is indexed by virtual address bits [4:0]. Then, the data,

excluding the cache-missed data which is written already, is read into the cache line on the

way which is selected to replace from the physical address space corresponding to the virtual

address. Data reading is performed, using the wraparound method, in order from the quad-

word data (8 bytes) including the cache-missed data. While the remaining data on the cache

line is being read, the CPU can execute the next processing. When reading of one line of data

is completed, the tag corresponding to the physical address is recorded in the cache, 1 is

written to the V bit and the U bit on the way. Then the LRU bit is updated to indicate the way

is latest one. Then the data in the write-back buffer is then written back to external memory.

A write of the specified access size is performed to the external memory corresponding to the

virtual address. In this case, a write to cache is not performed.