r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 23

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.4 Operation ........................................................................................................................... 936
23.5 Connection to PHY-LSI..................................................................................................... 984
23.6 Usage Notes ....................................................................................................................... 993
23.3.72 Transmit Descriptor List Start Address Register (TDLAR) ................................. 908
23.3.73 Receive Descriptor List Start Address Register (RDLAR)................................... 909
23.3.74 E-MAC/E-DMAC Status Register (EESR) .......................................................... 910
23.3.75 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR) ..................... 916
23.3.76 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 920
23.3.77 Receive Missed-Frame Counter Register (RMFCR) ............................................ 923
23.3.78 Transmit FIFO Threshold Register (TFTR).......................................................... 924
23.3.79 FIFO Depth Register (FDR) ................................................................................. 925
23.3.80 Receiving Method Control Register (RMCR) ...................................................... 926
23.3.81 Receive Descriptor Fetch Address Register (RDFAR)......................................... 927
23.3.82 Receive Descriptor Finished Address Register (RDFXR) .................................... 928
23.3.83 Receive Descriptor Final Flag Register (RDFFR) ................................................ 929
23.3.84 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 930
23.3.85 Transmit Descriptor Finished Address Register (TDFXR)................................... 931
23.3.86 Transmit Descriptor Final Flag Register (TDFFR)............................................... 932
23.3.87 Overflow Alert FIFO Threshold Register (FCFTR) ............................................. 933
23.3.88 Receive Data Padding Insert Register (RPADIR)................................................. 935
23.4.1 Descriptors and Descriptor List ............................................................................ 939
23.4.2 Transmission......................................................................................................... 956
23.4.3 Reception .............................................................................................................. 962
23.4.4 Relay ..................................................................................................................... 968
23.4.5 CAM Function ...................................................................................................... 969
23.4.6 Transmit/Receive Processing of Multi-Buffer Frame
23.4.7 Padding Insertion in Receive Data........................................................................ 973
23.4.8 Interrupt Processing .............................................................................................. 974
23.4.9 Activation Procedure ............................................................................................ 978
23.4.10 Flow Control......................................................................................................... 980
23.4.11 Magic Packet Detection ........................................................................................ 981
23.4.12 Direction for IEEE802.1Q Qtag............................................................................ 982
23.5.1 MII Frame Transmission/Reception Timing......................................................... 984
23.5.2 GMII/MII Frame Reception Timing ..................................................................... 986
23.5.3 RMII Frame Transmission/Reception Timing ...................................................... 988
23.5.4 Accessing MII Registers ....................................................................................... 989
23.5.5 Mll-RMII Interface Conversion ............................................................................ 991
23.6.1 Checksum Calculation of Ethernet Frames........................................................... 993
23.6.2 Notes on TSU Use ................................................................................................ 993
(Single-Frame/Multi-Descriptor) .......................................................................... 971
Rev. 1.00 Oct. 01, 2007 Page xxiii of lxvi