mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 110

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.11.3
The memory clock is supplied to the MT90502 by an external source. The memories are connected to an external
clock source which also must be coupled to the MT90502’s mem_clk pin. A frequency of 60 MHz for mem_clk is
recommended. Frequencies above 60 MHz will not increase performance, but will increase power consumption. At
lower clock frequencies, the MT90502 may not be able to operate at its full SAR capacity.
Upclk is used by CPU interface circuit. Its frequency should not be less than half of mem_clk. There is no
relationship between upclk to mem_clk.
0C0000h+SSB
100000h+SSB
080000h+SSB
180000h
Next
x00000h
Next
x00000h
000000h
080000h
000000h
100000h
+SSB
Mem_Clk and Upclk
One Bank 256 Channels
One Bank 128 Channels
1MB, 2MB, 3MB........ 24MB
1MB, 2MB, 3MB........ 24MB
0B, 512KB, 1MB or 2MB
0B, 512KB, 1MB or 2MB
CPS-Packet Descriptor
CPS-Packet Descriptor
Rx CID Table
LUT A, B & C
Rx CID Table
LUT A, B & C
SDRAM Silent
SDRAM Silent
512KB
256KB
Buffers
Buffers
Queue
Queue
The LUT start address is on the next available 1MB page.
SSB = SDRAM Silent Buffer
Figure 68 - SDRAM Memory Map for 128 and 256 Channels
100000h+SSB
080000h+SSB
Next
x00000h
000000h
100000h
Next
x00000h
000000h
080000h
Zarlink Semiconductor Inc.
MT90502
1MB, 2MB, 3MB........ 24MB
1MB, 2MB, 3MB........ 24MB
110
0B, 512KB, 1MB or 2MB
0B, 512KB, 1MB or 2MB
CPS-Packet Descriptor
CPS-Packet Descriptor
LUT A, B & C
SDRAM Silent
LUT A, B & C
SDRAM Silent
Buffers
Queue
Buffers
Queue
Two Banks 256 Channels
Two Banks 128 Channels
000000h
080000h
000000h
040000h
Rx CID Structure
Rx CID Structures
512KB
256KB
Data Sheet