mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 151
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
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Address: 62Ah
Label: porta_vci_mask
Reset Value: 0000h
vci_maska
Address: 62Ch
Label: porta_overflow0
Reset Value: FFFFh
ia_rx_cell_max
ia_oa_cell_max
ia_ob_cell_max
reserved
Address: 62Eh
Label: porta_overflow1
Reset Value: 000Fh
ia_oc_cell_max
reserved
Address: 630h
Label: porta_cell_arrival_high
Reset Value: 0000h
ia_arr[31:16]
Label
Label
Label
Label
Bit Position Type
Bit Position Type
15:0
Bit Position Type
Bit Position Type
15:0
13:10
15:14
15:4
3:0
5:0
9:6
RW For a cell from port A to be considered valid, any bits in its VCI whose
CNT Counter of the number of cells received from port A
Table 118 - Port A Cell Arrival Counter (High Word)
RW If the cell fill of the RX SAR output FIFO becomes greater than this value, cells
RW If the cell fill of the port A output FIFO becomes greater than this value, cells
RW If the cell fill of the port B output FIFO becomes greater than this value, cells
RW Reserved. Must always be “00”
RW If the cell fill of the port C output FIFO becomes greater than this value, cells
RW Reserved. Must always be “0000_0000_0000”
corresponding bits in this register are '1' must have the value contained in reg 628h.
Table 116 - Port A Overflow Register 0
Table 117 - Port A Overflow Register 1
from the port A input FIFO will be blocked. 3Fh = no backpressure
from the port A input FIFO will be blocked. Fh = no backpressure
from the port A input FIFO will be blocked. Fh = no backpressure
Table 115 - Port A VCI Mask Register
from the port A input FIFO will be blocked. Fh = no backpressure
Zarlink Semiconductor Inc.
MT90502
151
Description
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