mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 21

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.0
2.1
The MT90502 CPU module provides an interface permitting programmability from an external microprocessor or
CPU. The CPU module permits read/write access to the MT90502’s internal registers, internal memory and
external memories.
The CPU interface is comprised of the following:
The CPU interface can be configured to operate in either Intel or Motorola mode. The MT90502 supports both 8-bit
or 16-bit data bus and multiplexed or non-multiplexed address/data pins.
If the CPU is operating in 16-bit byte mode with the LSB of its address bus as a byte field, then the cpu_a[14:0] pins
of the MT90502 can be connected to the a[15:1] pins of the CPU. If both the MT90502 and the CPU are in 16-bit
word mode, then the cpu_a[14:0] pins should be connected to the a[14:0] pins of the CPU.
A reduced set of registers, the ‘CPU Interface Registers’ (000h to 00Ah), are employed to optimise access time and
to permit the CPU to execute indirect read/write accesses. The CPU also engages these registers to perform direct
read/write accesses. The MT90502 and CPU timing relationship is described in Section 4.3, “Intel/Motorola
Interface,” on page 185.
The CPU Control Register (100h) provides a software reset capability that allows the CPU to reset the MT90502
except for the CPU interface. The CPU interface can only be reset by a hardware reset.
2.1.1
The CPU interface provides a programmable global interrupt capability. The interrupt signal names are ‘interrupt1’
and ‘interrupt2’, pins AC2 and AC1 respectively. Both interrupts have programmability to select their polarity (open
collector drive) via registers ‘interrupt1_conf’ and ‘interrupt2_conf’, addresses 214h and 216h respectively.
Interrupt1 provides the capability to program a minimum acceptable period between interrupts. The period is
programmed in µs units via the ‘interrupt1_conf’ register. This provides a ‘frequency interrupt controller’ facility and
masks the assertion of further interrupts until the specified period of time has elapsed. The mask period will start
when the interrupt1_treated [15] bit in the register ‘interrupt_flags’ (address 210h) is set. When Interrupt2 is enabled
it is always activated when an interrupt condition occurs.
The operation of the CPU interrupt network is common for all modules. When an interrupt is asserted, an interrupt
flag is set to identify the module where the interrupt was generated. Each module has one or more Interrupt Enable
Registers where a set interrupt enable bit enables an interrupt source. On completion of the ISR the interrupt must
be cleared as the interrupt will remain asserted until it is de-asserted by the user. All Interrupt Enable Registers
have a mirror Status Register. Hence, the bit positioning of the interrupt enables and the corresponding status bits
are identical.
Note: Interrupt pins are always tri-stated when inactive.
2.1.1.1
Upon the initialisation of the Global Interrupt pins the following methodology is adopted to identify the source of the
interrupt. For this example Interrupt2 is employed and the CPU module will be the source of the interrupt.
[1] Direct Access Select (DAS) as the MSB bit concatenated with a 15-bit address bus
[2] 16-bit data bus
[3] 2 interrupt signals
[4] associated control signals.
CPU Interface
Functional Description
CPU Interrupts
Example Interrupt Flow
Zarlink Semiconductor Inc.
MT90502
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Data Sheet