mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 194
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
(204 pages)
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t3_muxed cpu_rdy_ndtack falling edge to cpu_ale rising edge
t3_reads cpu_rdy_ndtack falling edge to read_access_active rising
Symbol
t10
t15
t16
t17
t11
t1
t5
t8
t9
read_access_active falling edge to cpu_ale fall
edge
Read Access Time
read_access_active falling edge to cpu_d driven
read_access_active falling edge to cpu_rdy_ndtack driven
high
read_access_active rising edge to cpu_rdy_ndtack rising
edge
cpu_rdy_ndtack rising edge to cpu_rdy_ndtack tri-state
cpu_ale high pulse width
cpu_d valid to cpu_ale falling edge
cpu_ale falling edge to cpu_d invalid
Table 209 - Multiplexed CPU Interface - Motorola Mode - Read Access
Description
Zarlink Semiconductor Inc.
MT90502
194
3 * upclk - 4
Min.
0
0
0
0
2
5
5
5
Typical
2 * upclk - 4
Table 205
Max.
see
12
10
8
Data Sheet
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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