mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 136

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 428h
Label: crc_config0
Reset Value: FFFFh
crc_preset
Address: 42Ah
Label: crc_config1
Reset Value: F0B8h
crc_mask
Address: 430h
Label: aal0_manage
Reset Value: 0000h
rx_aal0_base_add
rx_aal0_buf_size
reserved
Address: 432h
Label: aal0_read
Reset Value: 0000h
rx_aal0_rpnt
reserved
Label
Label
Label
Label
Bit Position
Bit Position
Bit Position
Bit Position
15:12
11:0
15:12
15:0
15:0
11:9
8:0
Table 79 - AAL0 FIFO Management Register
Table 77 - CRC Configuration Register 0
Table 78 - CRC Configuration Register 1
Table 80 - AAL0 Read Pointer Register
RW
RW
Type
Type
Type
Type
RW
RW
RW
RW
RW
Zarlink Semiconductor Inc.
The CPU's read pointer to the AAL0 data cell FIFO. This read
pointer has an extra bit to allow for a full buffer (for example, 128
cells instead of 127)
Reserved. Must always be “0000”
MT90502
HDLC CRC End Mask. Must be “1111_0000_1011_1000” for
ITU compliance.
Represents bits 20:12 of the byte address at which the AAL0
data cell FIFO is mapped.
“000” = 4 KByte, “001” = 8 KB, “010” = 16 KB, “011” = 32 KB,
“100” = 64 KB, “101” = 128 KB, others = reserved
Reserved. Must always be “0000”
HDLC CRC Preset. Must be “1111_1111_1111_1111” for ITU
compliance.
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Description
Description
Description
Description
Data Sheet