mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 138

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 43Ch
Label: error_readure
Reset Value: 0000h
error_rpnt
reserved
Address: 440h
Label: cpu_manage0
Reset Value: 0000h
cpu_cpsp_base_add
cpu_cpsp_buf_size
reserved
Address: 442h
Label: cpu_manage1
Reset Value: 0000h
cpu_cpsp_rpnt
Address: 460h
Label: aal0_timeout_period_high
Reset Value: 0000h
aal0_timeout_period[19:16]
reserved
Label
Label
Label
Label
Bit Position
Table 87 - AAL0 Timeout Period (High Word) Register
Bit Position
Bit Position
14:0
Bit Position
15
15:9
15:0
6:0
8:7
Table 84 - Error Read Pointer Register
15:4
3:0
Table 85 - CPU Management Register 0
Table 86 - CPU Management Register 1
Type
RW
RW
Type
Type
RW
RW
RW
RW
Type
Zarlink Semiconductor Inc.
RW
RW
The CPU's read pointer to the error structure buffer. This
read pointer has an extra bit to allow for a full buffer (for
example, 1024 structures instead of 1023)
Reserved. Must always be “0”
MT90502
Bits 20:14 of the byte address at which the CPU-destined
CPS-Packet buffer is mapped.
“00” = 16 KByte, “01” = 32 KB, “10” = 64 KB, “11” = 128 KB
Reserved. Must always be “0000_000”
Word read pointer to the CPU-destined CPS-Packet buffer
Reserved. Must always be “0000_0000_0000”
If an AAL0 cell remains in the buffer for the period in this
register or more, an alarm will be generated. In us.
138
Description
Description
Description
Description
Data Sheet